GPUs, accelerators, compute markets and systems for AI workloads.
Showing 1–4 of 4 dossiers
CS-4 combines three WSE-3 Turbo wafers with Cerebras’ new Nexus rack design. The practical shift is architectural: compute, power and I/O become modular, while RoCE and direct wafer links open a path to faster deployment and disaggregated inference.
Cloud Run sandboxes now cover all resource types. The August 5 expansion matters for builders whose agents or automation run in batch jobs or continuously pulling workers rather than HTTP services, while the feature remains pre-GA and shares CPU and memory with the host container.
Render is reshaping Workflows economics as it reaches GA: most small and I/O-heavy tasks should get cheaper under Flex, while task-state retention becomes a new line item and fixed-size Pro tiers remain for heavier compute.
GPT-5.6 Sol Ultrafast remains in limited preview, but OpenAI’s August 21 standard-tier price cut changes its economics: Sol input is now 20% cheaper and output 33% cheaper through at least November 21. Ultrafast pricing is still undisclosed.
AI capability depends on physical infrastructure: accelerators, memory, networking, power and the software that turns them into usable compute. Supply constraints and platform strategy can shape model access and price long before most product teams touch the hardware directly.
BTN follows consequential developments across GPUs, custom chips, capacity markets and AI cloud services. Coverage explains the link between an infrastructure announcement and the choices available to builders using APIs, renting clusters or serving their own models. It looks for real availability and economics rather than peak specifications alone. The goal is a grounded view of what new compute changes upstream and where bottlenecks, lock-in or operational complexity remain.
Energy use, data-centre construction and export controls also affect where capacity appears and who can buy it. Those factors are covered when they change product access or market structure, without pretending every chip announcement has an immediate application-level consequence. The chain from hardware to API remains the useful frame.